Updated pic init
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43
kernel/cpu/pic.c
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43
kernel/cpu/pic.c
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//
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// Created by rick on 22-08-21.
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//
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#include <myke/cpu/pic.h>
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#include <myke/drivers/ports.h>
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// https://wiki.osdev.org/8259_PIC
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#define ICW1_ICW4 0x01 /* ICW4 (not) needed */
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#define ICW1_SINGLE 0x02 /* Single (cascade) mode */
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#define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */
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#define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */
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#define ICW1_INIT 0x10 /* Initialization - required! */
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#define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */
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#define ICW4_AUTO 0x02 /* Auto (normal) EOI */
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#define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */
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#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
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#define ICW4_SFNM 0x10 /* Special fully nested (not) */
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void pic_init() {
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// init both master and slave pic's
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port_byte_out(PORT_PIC_MASTER_COMMAND, ICW1_INIT | ICW1_ICW4);
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port_byte_out(PORT_PIC_SLAVE_COMMAND, ICW1_INIT | ICW1_ICW4);
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// master with ICW4 offset 20, Slave on IRQ2, 8086 mode,
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// ICW2
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port_byte_out(PORT_PIC_MASTER_DATA, 0x20); // offset master
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port_byte_out(PORT_PIC_SLAVE_DATA, 0x28); // offset slave
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// ICW3
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port_byte_out(PORT_PIC_MASTER_DATA, 0x04); // slave PIC at IRQ2
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port_byte_out(PORT_PIC_SLAVE_DATA, 0x02); // cascade identity
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// ICW4
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port_byte_out(PORT_PIC_MASTER_DATA, ICW4_8086); // 8086 mode
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port_byte_out(PORT_PIC_SLAVE_DATA, ICW4_8086);
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// empty mask
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pic_set_mask(0);
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}
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void pic_set_mask(uint16_t mask) {
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port_byte_out(PORT_PIC_MASTER_DATA, mask & 0xFF);
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port_byte_out(PORT_PIC_SLAVE_DATA, mask << 8);
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}
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