diff --git a/include/myke/cpu/cpuidx.h b/include/myke/cpu/cpuidx.h index 91d28ec..e55d099 100644 --- a/include/myke/cpu/cpuidx.h +++ b/include/myke/cpu/cpuidx.h @@ -7,74 +7,13 @@ #include -typedef struct { - bool sse3: 1; - bool pclmul: 1; - bool dtes64: 1; - bool monitor: 1; - bool ds_cpl: 1; - bool vmx: 1; - bool smx: 1; - bool est: 1; - bool tm2: 1; - bool ssse3: 1; - bool cid: 1; - bool reserved: 1; - bool fma: 1; - bool cx16: 1; - bool etprd: 1; - bool pdcm: 1; - bool pcide: 1; - bool dca: 1; - bool sse4_1: 1; - bool sse4_2: 1; - bool x2APIC: 1; - bool movbe: 1; - bool popcnt: 1; - bool reserved2: 1; - bool aes: 1; - bool xsave: 1; - bool osxsave: 1; - bool avx: 1; -} cpu_features_ecx; +enum { + CPUID_VENDOR_ID = 0x00, + CPUID_FEATURE_FLAGS = 0x01, + CPUID_CACHE +}; -typedef struct { - bool fpu: 1; - bool vme: 1; - bool de: 1; - bool pse: 1; - bool tsc: 1; - bool msr: 1; - bool pae: 1; - bool mce: 1; - bool cx8: 1; - bool apic: 1; - bool reserved: 1; - bool sep: 1; - bool mtrr: 1; - bool pge: 1; - bool mca: 1; - bool cmov: 1; - bool pat: 1; - bool pse36: 1; - bool psn: 1; - bool clf: 1; - bool reserved2: 1; - bool dtes: 1; - bool acpi: 1; - bool mmx: 1; - bool fxsr: 1; - bool sse: 1; - bool sse2: 1; - bool ss: 1; - bool htt: 1; - bool tm1: 1; - bool ia64: 1; - bool pbe: 1; - -} cpu_features_edx; - -enum cpu_features { +enum { CPUID_FEAT_ECX_SSE3 = 1 << 0, CPUID_FEAT_ECX_PCLMUL = 1 << 1, CPUID_FEAT_ECX_DTES64 = 1 << 2, @@ -134,6 +73,8 @@ enum cpu_features { CPUID_FEAT_EDX_PBE = 1 << 31 }; +static bool has_apic(); + void cpuidx_print_info(); #endif //NEW_KERNEL_CPUIDX_H diff --git a/include/myke/cpu/pic.h b/include/myke/cpu/pic.h new file mode 100644 index 0000000..87911f5 --- /dev/null +++ b/include/myke/cpu/pic.h @@ -0,0 +1,14 @@ +// +// Created by rick on 22-08-21. +// + +#ifndef NEW_KERNEL_PIC_H +#define NEW_KERNEL_PIC_H + +#include + +void pic_init(); + +void pic_set_mask(uint16_t mask); + +#endif //NEW_KERNEL_PIC_H diff --git a/kernel/cpu/cpuidx.c b/kernel/cpu/cpuidx.c index a0579f1..25ece85 100644 --- a/kernel/cpu/cpuidx.c +++ b/kernel/cpu/cpuidx.c @@ -16,18 +16,16 @@ union cpu_name { }; }; +static bool has_apic() { + uint32_t eax, unused, edx; + __get_cpuid(CPUID_FEATURE_FLAGS, &eax, &unused, &unused, &edx); + return edx & CPUID_FEAT_EDX_APIC; +} + void cpuidx_print_info() { union cpu_name name; - __get_cpuid(0, NULL, &name.parts[0], &name.parts[2], &name.parts[1]); + __get_cpuid(CPUID_VENDOR_ID, NULL, &name.parts[0], &name.parts[2], &name.parts[1]); name.end = 0; printf("CPU: %s\n", &name.name); - - cpu_features_ecx features_ecx; - cpu_features_edx features_edx; - __get_cpuid(1, NULL, NULL, (uint32_t *) &features_ecx, (uint32_t *) &features_edx); - - printf(""); - - } diff --git a/kernel/cpu/isr.c b/kernel/cpu/isr.c index e14da65..1f4ce18 100644 --- a/kernel/cpu/isr.c +++ b/kernel/cpu/isr.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -52,19 +53,10 @@ void isr_install() { // Remap the PIC // todo make readable - port_byte_out(0x20, 0x11); - port_byte_out(0xA0, 0x11); - port_byte_out(0x21, 0x20); - port_byte_out(0xA1, 0x28); - port_byte_out(0x21, 0x04); - port_byte_out(0xA1, 0x02); - port_byte_out(0x21, 0x01); - port_byte_out(0xA1, 0x01); - port_byte_out(0x21, 0x0); - port_byte_out(0xA1, 0x0); + pic_init(); // Install the IRQs - set_idt_gate(32, (uint32_t) irq0); + set_idt_gate(32, (uint32_t) irq0); // 0x20 set_idt_gate(33, (uint32_t) irq1); set_idt_gate(34, (uint32_t) irq2); set_idt_gate(35, (uint32_t) irq3); @@ -72,7 +64,7 @@ void isr_install() { set_idt_gate(37, (uint32_t) irq5); set_idt_gate(38, (uint32_t) irq6); set_idt_gate(39, (uint32_t) irq7); - set_idt_gate(40, (uint32_t) irq8); + set_idt_gate(40, (uint32_t) irq8); // 0x28 set_idt_gate(41, (uint32_t) irq9); set_idt_gate(42, (uint32_t) irq10); set_idt_gate(43, (uint32_t) irq11); diff --git a/kernel/cpu/pic.c b/kernel/cpu/pic.c new file mode 100644 index 0000000..4c83b70 --- /dev/null +++ b/kernel/cpu/pic.c @@ -0,0 +1,43 @@ +// +// Created by rick on 22-08-21. +// +#include +#include + +// https://wiki.osdev.org/8259_PIC +#define ICW1_ICW4 0x01 /* ICW4 (not) needed */ +#define ICW1_SINGLE 0x02 /* Single (cascade) mode */ +#define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */ +#define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */ +#define ICW1_INIT 0x10 /* Initialization - required! */ + +#define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */ +#define ICW4_AUTO 0x02 /* Auto (normal) EOI */ +#define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */ +#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */ +#define ICW4_SFNM 0x10 /* Special fully nested (not) */ + +void pic_init() { + // init both master and slave pic's + port_byte_out(PORT_PIC_MASTER_COMMAND, ICW1_INIT | ICW1_ICW4); + port_byte_out(PORT_PIC_SLAVE_COMMAND, ICW1_INIT | ICW1_ICW4); + + // master with ICW4 offset 20, Slave on IRQ2, 8086 mode, + // ICW2 + port_byte_out(PORT_PIC_MASTER_DATA, 0x20); // offset master + port_byte_out(PORT_PIC_SLAVE_DATA, 0x28); // offset slave + // ICW3 + port_byte_out(PORT_PIC_MASTER_DATA, 0x04); // slave PIC at IRQ2 + port_byte_out(PORT_PIC_SLAVE_DATA, 0x02); // cascade identity + // ICW4 + port_byte_out(PORT_PIC_MASTER_DATA, ICW4_8086); // 8086 mode + port_byte_out(PORT_PIC_SLAVE_DATA, ICW4_8086); + + // empty mask + pic_set_mask(0); +} + +void pic_set_mask(uint16_t mask) { + port_byte_out(PORT_PIC_MASTER_DATA, mask & 0xFF); + port_byte_out(PORT_PIC_SLAVE_DATA, mask << 8); +} \ No newline at end of file