691 lines
24 KiB
C
691 lines
24 KiB
C
//
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// Created by rick on 03-02-21.
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//
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// https://wiki.osdev.org/PCI_IDE_Controller
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#include "ide.h"
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#include "ports.h"
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#include <types.h>
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#include <libk/kprint.h>
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#include <drivers/pci.h>
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#include <stdbool.h>
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#include <libk/libk.h>
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#include <cpu/timer.h>
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#include <libc/kprintf.h>
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#include <fs/blockdev.h>
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#include <mem/malloc.h>
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#include <tasks/locking.h>
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#define ATA_SR_BSY 0x80 // Busy
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#define ATA_SR_DRDY 0x40 // Drive ready
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#define ATA_SR_DF 0x20 // Drive write fault
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#define ATA_SR_DSC 0x10 // Drive seek complete
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#define ATA_SR_DRQ 0x08 // Data request ready
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#define ATA_SR_CORR 0x04 // Corrected data
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#define ATA_SR_IDX 0x02 // Index
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#define ATA_SR_ERR 0x01 // Error
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#define ATA_ER_BBK 0x80 // Bad block
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#define ATA_ER_UNC 0x40 // Uncorrectable data
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#define ATA_ER_MC 0x20 // Media changed
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#define ATA_ER_IDNF 0x10 // ID mark not found
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#define ATA_ER_MCR 0x08 // Media change request
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#define ATA_ER_ABRT 0x04 // Command aborted
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#define ATA_ER_TK0NF 0x02 // Track 0 not found
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#define ATA_ER_AMNF 0x01 // No address mark
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#define ATA_CMD_READ_PIO 0x20
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#define ATA_CMD_READ_PIO_EXT 0x24
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#define ATA_CMD_READ_DMA 0xC8
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#define ATA_CMD_READ_DMA_EXT 0x25
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#define ATA_CMD_WRITE_PIO 0x30
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#define ATA_CMD_WRITE_PIO_EXT 0x34
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#define ATA_CMD_WRITE_DMA 0xCA
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#define ATA_CMD_WRITE_DMA_EXT 0x35
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#define ATA_CMD_CACHE_FLUSH 0xE7
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#define ATA_CMD_CACHE_FLUSH_EXT 0xEA
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#define ATA_CMD_PACKET 0xA0
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#define ATA_CMD_IDENTIFY_PACKET 0xA1
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#define ATA_CMD_IDENTIFY 0xEC
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#define ATAPI_CMD_READ 0xA8
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#define ATAPI_CMD_EJECT 0x1B
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#define ATA_IDENT_DEVICETYPE 0
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#define ATA_IDENT_CYLINDERS 2
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#define ATA_IDENT_HEADS 6
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#define ATA_IDENT_SECTORS 12
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#define ATA_IDENT_SERIAL 20
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#define ATA_IDENT_MODEL 54
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#define ATA_IDENT_CAPABILITIES 98
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#define ATA_IDENT_FIELDVALID 106
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#define ATA_IDENT_MAX_LBA 120
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#define ATA_IDENT_COMMANDSETS 164
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#define ATA_IDENT_MAX_LBA_EXT 200
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#define ATA_CAP_LBA 0x200
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#define ATA_LBA28_MAX 0x10000000
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#define ATA_HDDDEVSEL_CHS 0b00000000
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#define ATA_HDDDEVSEL_LBA 0b01000000
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#define ATA_HDDDEVSEL_DEFAULT 0b10100000
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#define IDE_ATA 0x00
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#define IDE_ATAPI 0x01
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#define ATA_MASTER 0x00
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#define ATA_SLAVE 0x01
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// base
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#define ATA_REG_DATA 0x00
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#define ATA_REG_ERROR 0x01
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#define ATA_REG_FEATURES 0x01
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#define ATA_REG_SECCOUNT0 0x02
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#define ATA_REG_LBA0 0x03
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#define ATA_REG_LBA1 0x04
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#define ATA_REG_LBA2 0x05
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#define ATA_REG_HDDEVSEL 0x06
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#define ATA_REG_COMMAND 0x07
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#define ATA_REG_STATUS 0x07
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// ??
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#define ATA_REG_SECCOUNT1 0x12
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#define ATA_REG_LBA3 0x13
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#define ATA_REG_LBA4 0x14
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#define ATA_REG_LBA5 0x15
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// ctrl
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#define ATA_REG_CONTROL 0x22
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#define ATA_REG_ALTSTATUS 0x22
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#define ATA_REG_DEVADDRESS 0x23
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// Channels:
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#define ATA_PRIMARY 0x00
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#define ATA_SECONDARY 0x01
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// Directions:
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#define ATA_READ 0x00
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#define ATA_WRITE 0x01
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struct ide_channel_registers {
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unsigned short base; // I/O Base.
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unsigned short ctrl; // Control Base
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unsigned short bmide; // Bus Master IDE
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unsigned char nIEN; // nIEN (No Interrupt);
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} channels[2];
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unsigned char ide_buf[2048] = {0};
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unsigned static char ide_irq_invoked = 0;
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unsigned static char atapi_packet[12] = {0xA8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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struct ide_device {
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unsigned char reserved; // 0 (Empty) or 1 (This Drive really exists).
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unsigned char channel; // 0 (Primary Channel) or 1 (Secondary Channel).
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unsigned char drive; // 0 (Master Drive) or 1 (Slave Drive).
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unsigned short type; // 0: ATA, 1:ATAPI.
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unsigned short signature; // Drive Signature
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unsigned short capabilities;// Features.
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unsigned int commandSets; // Command Sets Supported.
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unsigned int size; // Size in Sectors.
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unsigned char model[41]; // Model in string.
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} ide_devices[4];
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typedef struct {
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uint8_t device_number: 2;
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uint8_t print_error: 1;
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} ide_block_device_info;
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mutex_t *ide_lock = NULL;
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uint8_t ide_read(uint8_t channel, uint8_t reg);
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void ide_write(uint8_t channel, uint8_t reg, uint8_t data);
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uint8_t ide_read(uint8_t channel, uint8_t reg) {
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uint8_t result;
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if (reg & 0x10) {
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ide_write(channel, ATA_REG_CONTROL, 0x80 | channels[channel].nIEN);
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result = port_byte_in(channels[channel].base + (reg & 0xF));
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ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);
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} else if (reg & 0x20) {
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result = port_byte_in(channels[channel].ctrl + (reg & 0xF));
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} else {
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result = port_byte_in(channels[channel].base + reg);
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}
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// if (reg < 0x08)
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// result = port_byte_in(channels[channel].base + reg - 0x00);
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// else if (reg < 0x0C)
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// result = port_byte_in(channels[channel].base + reg - 0x06);
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// else if (reg < 0x0E)
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// result = port_byte_in(channels[channel].ctrl + reg - 0x0A);
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// else if (reg < 0x16)
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// result = port_byte_in(channels[channel].bmide + reg - 0x0E); // todo this case is not handled in new code
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// if (reg > 0x07 && reg < 0x0C)
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// ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);
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return result;
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}
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void ide_write(uint8_t channel, uint8_t reg, uint8_t data) {
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if (reg & 0x10) {
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ide_write(channel, ATA_REG_CONTROL, 0x80 | channels[channel].nIEN);
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port_byte_out(channels[channel].base + (reg & 0xF), data);
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ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);
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} else if (reg & 0x20) {
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port_byte_out(channels[channel].ctrl + (reg & 0xF), data);
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} else {
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port_byte_out(channels[channel].base + reg, data);
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}
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// if (reg > 0x07 && reg < 0x0C)
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// ide_write(channel, ATA_REG_CONTROL, 0x80 | channels[channel].nIEN);
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// if (reg < 0x08)
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// port_byte_out(channels[channel].base + reg - 0x00, data);
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// else if (reg < 0x0C)
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// port_byte_out(channels[channel].base + reg - 0x06, data);
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// else if (reg < 0x0E)
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// port_byte_out(channels[channel].ctrl + reg - 0x0A, data);
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// else if (reg < 0x16)
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// port_byte_out(channels[channel].bmide + reg - 0x0E, data); // todo this case is not handled
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// if (reg > 0x07 && reg < 0x0C)
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// ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);
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}
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void ide_read_buffer(unsigned char channel, unsigned char reg, unsigned int *buffer, unsigned int quads) {
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/* WARNING: This code contains a serious bug. The inline assembly trashes ES and
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* ESP for all of the code the compiler generates between the inline
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* assembly blocks.
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*/
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if (reg & 0x10) {
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ide_write(channel, ATA_REG_CONTROL, 0x80 | channels[channel].nIEN);
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port_double_word_in_repeat(channels[channel].base + (reg & 0xF), buffer, quads);
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ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);
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} else if (reg & 0x20) {
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port_double_word_in_repeat(channels[channel].base + (reg & 0xF), buffer, quads);
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} else {
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port_double_word_in_repeat(channels[channel].base + reg, buffer, quads);
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}
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// if (reg > 0x07 && reg < 0x0C) {
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// ide_write(channel, ATA_REG_CONTROL, 0x80 | channels[channel].nIEN);
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// }
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// this assembly is probably necessary when reading paging
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// asm("pushw %es; movw %ds, %ax; movw %ax, %es" );
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// if (reg < 0x08) {
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// port_double_word_in_repeat(channels[channel].base + reg - 0x00, buffer, quads);
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// } else if (reg < 0x0C) {
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// port_double_word_in_repeat(channels[channel].base + reg - 0x06, buffer, quads);
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// } else if (reg < 0x0E) {
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// port_double_word_in_repeat(channels[channel].ctrl + reg - 0x0A, buffer, quads);
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// } else if (reg < 0x16) {
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// port_double_word_in_repeat(channels[channel].bmide + reg - 0x0E, buffer, quads);
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// }
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// asm("popw %es;");
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// if (reg > 0x07 && reg < 0x0C) {
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// ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);
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// }
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}
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unsigned char ide_polling(unsigned char channel, uint8_t advanced_check) {
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// (I) Delay 400 nanosecond for BSY to be set:
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// -------------------------------------------------
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for (int i = 0; i < 4; i++)
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ide_read(channel, ATA_REG_ALTSTATUS); // Reading the Alternate Status port wastes 100ns; loop four times.
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// (II) Wait for BSY to be cleared:
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// -------------------------------------------------
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while (ide_read(channel, ATA_REG_STATUS) & ATA_SR_BSY); // Wait for BSY to be zero.
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if (advanced_check) {
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unsigned char state = ide_read(channel, ATA_REG_STATUS); // Read Status Register.
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// (III) Check For Errors:
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// -------------------------------------------------
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if (state & ATA_SR_ERR)
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return 2; // Error.
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// (IV) Check If Device fault:
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// -------------------------------------------------
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if (state & ATA_SR_DF)
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return 1; // Device Fault.
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// (V) Check DRQ:
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// -------------------------------------------------
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// BSY = 0; DF = 0; ERR = 0 so we should check for DRQ now.
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if ((state & ATA_SR_DRQ) == 0)
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return 3; // DRQ should be set
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}
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return 0; // No Error.
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}
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unsigned char ide_print_error(unsigned int drive, unsigned char err) {
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if (err == 0)
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return err;
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kprint("IDE:");
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if (err == 1) {
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kprint("- Device Fault ");
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err = 19;
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} else if (err == 2) {
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unsigned char st = ide_read(ide_devices[drive].channel, ATA_REG_ERROR);
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if (st & ATA_ER_AMNF) {
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kprint("- No Address Mark Found - ");
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err = 7;
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}
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if (st & ATA_ER_TK0NF) {
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kprint("- No Media or Media Error - ");
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err = 3;
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}
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if (st & ATA_ER_ABRT) {
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kprint("- Command Aborted - ");
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err = 20;
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}
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if (st & ATA_ER_MCR) {
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kprint("- No Media or Media Error - ");
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err = 3;
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}
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if (st & ATA_ER_IDNF) {
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kprint("- ID mark not Found - ");
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err = 21;
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}
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if (st & ATA_ER_MC) {
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kprint("- No Media or Media Error - ");
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err = 3;
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}
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if (st & ATA_ER_UNC) {
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kprint("- Uncorrectable Data Error - ");
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err = 22;
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}
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if (st & ATA_ER_BBK) {
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kprint("- Bad Sectors - ");
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err = 13;
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}
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} else if (err == 3) {
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kprint("- Reads Nothing - ");
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err = 23;
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} else if (err == 4) {
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kprint("- Write Protected - ");
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err = 8;
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} else if (err & 0xF0) {
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if (err == 0xF1) {
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kprint("- Unsupported operation by driver - ");
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} else {
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kprint(" - Unknown driver error - ");
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}
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}
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printf(" - [%s %s] %s\n",
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((const char *[]) {"Primary", "Secondary"}[ide_devices[drive].channel]),
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((const char *[]) {"Master", "Slave"}[ide_devices[drive].drive]),
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&ide_devices[drive].model);
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return err;
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}
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uint8_t ide_pci_validate(const pci_device *device);
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uint8_t ide_pci_initialize(pci_device *device);
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const pci_driver ide_pci_driver = {
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.name = "pci-ide",
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.description = "Default PCI IDE Driver",
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.order = 0xFF, // let other block_dev_drivers precede if they can
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.pci_use_subclass = true,
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.pci_class = PCI_CLASS_MASS_STORAGE,
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.pci_subclass = PCI_SUB_CLASS_IDE,
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.validate = ide_pci_validate,
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.initialize = ide_pci_initialize,
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};
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uint8_t ide_pci_validate(const pci_device *device) {
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if (device->class != PCI_CLASS_MASS_STORAGE
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|| device->subclass != PCI_SUB_CLASS_IDE
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|| (device->programInterface != 0x8A && device->programInterface != 0x80)) {
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return PCI_VALIDATE_FAIL;
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}
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// todo other validations
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return PCI_VALIDATE_OK;
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}
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void ide_fix_bar(bar_info *bar, uint32_t default_address, uint32_t size) {
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if (bar->address == 0x0) {
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// no need to actually write ti back
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bar->address = default_address;
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bar->prefetchable = 0;
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bar->type = 0;
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bar->is_io_space = 1;
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bar->size = size;
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}
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}
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bool ide_pci_init_channels(pci_device *device) {
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pci_config_write_byte(device->bus, device->slot, device->func, PCI_CONFIG_INTERRUPT_LINE, 0xFE);
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if (pci_config_read_byte(device->bus, device->slot, device->func, PCI_CONFIG_INTERRUPT_LINE) == 0xFE) {
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#ifdef IDE_ENABLE_INTERRUPT
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k_panics("NOT SUPPORTED");
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#else
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pci_config_write_byte(device->bus, device->slot, device->func, PCI_CONFIG_INTERRUPT_LINE,
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PCI_INTERRUPT_LINE_DISABLED);
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#endif
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}
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pci_init_bar(device, 0);
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pci_init_bar(device, 1);
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pci_init_bar(device, 2);
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pci_init_bar(device, 3);
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pci_init_bar(device, 4);
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if (!device->bar0.present
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|| !device->bar1.present
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|| !device->bar2.present
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|| !device->bar3.present
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|| !device->bar4.present) {
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k_panics("IDE Missing bars");
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return false;
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}
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ide_fix_bar(&device->bar0, 0x1F0, 8);
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ide_fix_bar(&device->bar1, 0x3F6, 4);
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ide_fix_bar(&device->bar2, 0x170, 8);
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ide_fix_bar(&device->bar3, 0x376, 4);
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channels[ATA_PRIMARY].base = device->bar0.address;
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channels[ATA_PRIMARY].ctrl = device->bar1.address;
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channels[ATA_SECONDARY].base = device->bar2.address;
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channels[ATA_SECONDARY].ctrl = device->bar3.address;
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channels[ATA_PRIMARY].bmide = device->bar4.address + 0; // Bus Master IDE
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channels[ATA_SECONDARY].bmide = device->bar4.address + 8; // Bus Master IDE
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return true;
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}
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uint8_t ide_block_dev_access(const block_device *device, uint8_t direction, uint32_t lba, uint8_t sectors, void *target) {
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ide_block_device_info *info = device->device_info;
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uint8_t result = ide_access(direction, info->device_number, lba, sectors, target);
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if (result != 0) {
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if (info->print_error) {
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ide_print_error(info->device_number, result);
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}
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return BLOCK_DEV_ACCESS_ERR;
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}
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return BLOCK_DEV_ACCESS_OK;
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}
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void ide_register_block_devices() {
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for (int i = 0; i < 3; ++i) {
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if (!ide_devices[i].reserved) {
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continue;
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}
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ide_block_device_info *info = malloc(sizeof(ide_block_device_info)); // todo free for this one
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info->device_number = i;
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info->print_error = 1;
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block_device device = {
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.flags.present = 1,
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.flags.root_device = 1,
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.device_info = info,
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.num_lba = ide_devices[i].size,
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.block_size = 0x200,
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.access = ide_block_dev_access,
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};
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sprintf(device.identifier, "ide%d", i);
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block_dev_register(&device);
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break;
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}
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}
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uint8_t ide_pci_initialize(pci_device *device) {
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if (!ide_pci_init_channels(device)) {
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return PCI_INIT_FAIL;
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}
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if (ide_lock != NULL) {
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k_panics("IDE already initialized\n");
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}
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ide_lock = mutex_create();
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mutex_acquire(ide_lock);
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// disable IRQ
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ide_write(ATA_PRIMARY, ATA_REG_CONTROL, 2);
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ide_write(ATA_SECONDARY, ATA_REG_CONTROL, 2);
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int count = 0;
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// 3- Detect ATA-ATAPI Devices:
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for (int i = 0; i < 2; i++) {
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for (int j = 0; j < 2; j++) {
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unsigned char err = 0, type = IDE_ATA, status;
|
|
ide_devices[count].reserved = 0; // Assuming that no drive here.
|
|
|
|
// (I) Select Drive:
|
|
ide_write(i, ATA_REG_HDDEVSEL, 0xA0 | (j << 4)); // Select Drive.
|
|
sleep(1); // Wait 1ms for drive select to work.
|
|
|
|
// (II) Send ATA Identify Command:
|
|
ide_write(i, ATA_REG_COMMAND, ATA_CMD_IDENTIFY);
|
|
sleep(1); // This function should be implemented in your OS. which waits for 1 ms.
|
|
// it is based on System Timer Device Driver.
|
|
|
|
// (III) Polling:
|
|
if (ide_read(i, ATA_REG_STATUS) == 0) continue; // If Status = 0, No Device.
|
|
|
|
while (1) {
|
|
status = ide_read(i, ATA_REG_STATUS);
|
|
if ((status & ATA_SR_ERR)) {
|
|
err = 1;
|
|
break;
|
|
} // If Err, Device is not ATA.
|
|
if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRQ)) break; // Everything is right.
|
|
}
|
|
|
|
// (IV) Probe for ATAPI Devices:
|
|
|
|
if (err != 0) {
|
|
unsigned char cl = ide_read(i, ATA_REG_LBA1);
|
|
unsigned char ch = ide_read(i, ATA_REG_LBA2);
|
|
|
|
if (cl == 0x14 && ch == 0xEB) {
|
|
type = IDE_ATAPI;
|
|
} else if (cl == 0x69 && ch == 0x96) {
|
|
type = IDE_ATAPI;
|
|
} else {
|
|
continue; // Unknown Type (may not be a device).
|
|
}
|
|
|
|
ide_write(i, ATA_REG_COMMAND, ATA_CMD_IDENTIFY_PACKET);
|
|
sleep(1);
|
|
}
|
|
|
|
// (V) Read Identification Space of the Device:
|
|
ide_read_buffer(i, ATA_REG_DATA, (unsigned int *) ide_buf, 128);
|
|
|
|
// (VI) Read Device Parameters:
|
|
ide_devices[count].reserved = 1;
|
|
ide_devices[count].type = type;
|
|
ide_devices[count].channel = i;
|
|
ide_devices[count].drive = j;
|
|
ide_devices[count].signature = *((unsigned short *) (ide_buf + ATA_IDENT_DEVICETYPE));
|
|
ide_devices[count].capabilities = *((unsigned short *) (ide_buf + ATA_IDENT_CAPABILITIES));
|
|
ide_devices[count].commandSets = *((unsigned int *) (ide_buf + ATA_IDENT_COMMANDSETS));
|
|
|
|
// (VII) Get Size:
|
|
if (ide_devices[count].commandSets & (1 << 26))
|
|
// Device uses 48-Bit Addressing:
|
|
ide_devices[count].size = *((unsigned int *) (ide_buf + ATA_IDENT_MAX_LBA_EXT));
|
|
else
|
|
// Device uses CHS or 28-bit Addressing:
|
|
ide_devices[count].size = *((unsigned int *) (ide_buf + ATA_IDENT_MAX_LBA));
|
|
|
|
// (VIII) String indicates model of device (like Western Digital HDD and SONY DVD-RW...):
|
|
for (int k = 0; k < 40; k += 2) {
|
|
ide_devices[count].model[k] = ide_buf[ATA_IDENT_MODEL + k + 1];
|
|
ide_devices[count].model[k + 1] = ide_buf[ATA_IDENT_MODEL + k];
|
|
}
|
|
ide_devices[count].model[40] = 0; // Terminate String.
|
|
|
|
count++;
|
|
}
|
|
}
|
|
mutex_release(ide_lock);
|
|
ide_register_block_devices();
|
|
|
|
return PCI_INIT_OK;
|
|
}
|
|
|
|
void ide_print_devices() {
|
|
for (int i = 0; i < 4; i++) {
|
|
if (ide_devices[i].reserved == 1) {
|
|
printf("Drive %d: %s Drive %dMB - %s\n",
|
|
i,
|
|
((const char *[]) {"ATA", "ATAPI"}[ide_devices[i].type]),
|
|
ide_devices[i].size / 1024 / 2,
|
|
ide_devices[i].model);
|
|
} else {
|
|
printf("Drive %d disconnected\n", i);
|
|
}
|
|
}
|
|
}
|
|
|
|
void ide_register() {
|
|
pci_register_driver(&ide_pci_driver);
|
|
}
|
|
|
|
uint8_t ide_read_ata_access(uint8_t direction, uint8_t drive, uint32_t lba, uint8_t numsects, void *target) {
|
|
uint8_t lba_mode /* 0: CHS, 1:LBA28, 2: LBA48 */, dma /* 0: No DMA, 1: DMA */, cmd;
|
|
uint8_t lba_io[6];
|
|
uint8_t channel = ide_devices[drive].channel;
|
|
uint8_t slavebit = ide_devices[drive].drive;
|
|
uint32_t bus = channels[channel].base;
|
|
uint32_t words = 256;
|
|
uint16_t cyl, i;
|
|
uint8_t head, sect, err;
|
|
|
|
ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN = (ide_irq_invoked = 0x0) + 0x02);
|
|
|
|
// setup LBA data
|
|
if (lba >= ATA_LBA28_MAX) { // Sure Drive should support LBA in this case, or you are
|
|
// giving a wrong LBA.
|
|
// LBA48:
|
|
lba_mode = 2;
|
|
lba_io[0] = (lba & 0x000000FF) >> 0;
|
|
lba_io[1] = (lba & 0x0000FF00) >> 8;
|
|
lba_io[2] = (lba & 0x00FF0000) >> 16;
|
|
lba_io[3] = (lba & 0xFF000000) >> 24;
|
|
lba_io[4] = 0; // LBA28 is integer, so 32-bits are enough to access 2TB.
|
|
lba_io[5] = 0; // LBA28 is integer, so 32-bits are enough to access 2TB.
|
|
head = 0; // Lower 4-bits of HDDEVSEL are not used here.
|
|
} else if (ide_devices[drive].capabilities & ATA_CAP_LBA) { // Drive supports LBA?
|
|
// LBA28:
|
|
lba_mode = 1;
|
|
lba_io[0] = (lba & 0x00000FF) >> 0;
|
|
lba_io[1] = (lba & 0x000FF00) >> 8;
|
|
lba_io[2] = (lba & 0x0FF0000) >> 16;
|
|
lba_io[3] = 0; // These Registers are not used here.
|
|
lba_io[4] = 0; // These Registers are not used here.
|
|
lba_io[5] = 0; // These Registers are not used here.
|
|
head = (lba & 0xF000000) >> 24;
|
|
} else {
|
|
// CHS:
|
|
lba_mode = 0;
|
|
sect = (lba % 63) + 1;
|
|
cyl = (lba + 1 - sect) / (16 * 63);
|
|
lba_io[0] = sect;
|
|
lba_io[1] = (cyl >> 0) & 0xFF;
|
|
lba_io[2] = (cyl >> 8) & 0xFF;
|
|
lba_io[3] = 0;
|
|
lba_io[4] = 0;
|
|
lba_io[5] = 0;
|
|
head = (lba + 1 - sect) % (16 * 63) / (63); // Head number is written to HDDEVSEL lower 4-bits.
|
|
}
|
|
|
|
// check if DMA is available
|
|
dma = 0; // maybe later
|
|
|
|
// wait for the drive to have time for us
|
|
while (ide_read(channel, ATA_REG_STATUS) & ATA_SR_BSY) {}
|
|
|
|
if (lba_mode == 0) {
|
|
ide_write(channel,
|
|
ATA_REG_HDDEVSEL,
|
|
ATA_HDDDEVSEL_DEFAULT | ATA_HDDDEVSEL_CHS | (slavebit << 4) | head); // Drive & CHS.
|
|
} else {
|
|
ide_write(channel,
|
|
ATA_REG_HDDEVSEL,
|
|
ATA_HDDDEVSEL_DEFAULT | ATA_HDDDEVSEL_LBA | (slavebit << 4) | head); // Drive & LBA
|
|
}
|
|
|
|
// store data
|
|
if (lba_mode == 2) {
|
|
ide_write(channel, ATA_REG_SECCOUNT1, 0);
|
|
ide_write(channel, ATA_REG_LBA3, lba_io[3]);
|
|
ide_write(channel, ATA_REG_LBA4, lba_io[4]);
|
|
ide_write(channel, ATA_REG_LBA5, lba_io[5]);
|
|
}
|
|
ide_write(channel, ATA_REG_SECCOUNT0, numsects);
|
|
ide_write(channel, ATA_REG_LBA0, lba_io[0]);
|
|
ide_write(channel, ATA_REG_LBA1, lba_io[1]);
|
|
ide_write(channel, ATA_REG_LBA2, lba_io[2]);
|
|
|
|
// pick correct ccommand
|
|
if (lba_mode == 0 && dma == 0 && direction == 0) cmd = ATA_CMD_READ_PIO;
|
|
if (lba_mode == 1 && dma == 0 && direction == 0) cmd = ATA_CMD_READ_PIO;
|
|
if (lba_mode == 2 && dma == 0 && direction == 0) cmd = ATA_CMD_READ_PIO_EXT;
|
|
// if (lba_mode == 0 && dma == 1 && direction == 0) cmd = ATA_CMD_READ_DMA;
|
|
// if (lba_mode == 1 && dma == 1 && direction == 0) cmd = ATA_CMD_READ_DMA;
|
|
// if (lba_mode == 2 && dma == 1 && direction == 0) cmd = ATA_CMD_READ_DMA_EXT;
|
|
if (lba_mode == 0 && dma == 0 && direction == 1) cmd = ATA_CMD_WRITE_PIO;
|
|
if (lba_mode == 1 && dma == 0 && direction == 1) cmd = ATA_CMD_WRITE_PIO;
|
|
if (lba_mode == 2 && dma == 0 && direction == 1) cmd = ATA_CMD_WRITE_PIO_EXT;
|
|
// if (lba_mode == 0 && dma == 1 && direction == 1) cmd = ATA_CMD_WRITE_DMA;
|
|
// if (lba_mode == 1 && dma == 1 && direction == 1) cmd = ATA_CMD_WRITE_DMA;
|
|
// if (lba_mode == 2 && dma == 1 && direction == 1) cmd = ATA_CMD_WRITE_DMA_EXT;
|
|
ide_write(channel, ATA_REG_COMMAND, cmd); // Send the Command.
|
|
|
|
void *cur_addr = target;
|
|
// read response
|
|
if (dma) {
|
|
if (direction == 0);
|
|
// DMA Read.
|
|
else;
|
|
// DMA Write.
|
|
} else {
|
|
if (direction == 0) {
|
|
// PIO Read.
|
|
for (i = 0; i < numsects; i++) {
|
|
if ((err = ide_polling(channel, 1))) {
|
|
ide_print_error(drive, err);
|
|
return err; // Polling, set error and exit if there is.
|
|
}
|
|
port_word_in_repeat(bus, cur_addr, words);
|
|
cur_addr += (words * 2);
|
|
}
|
|
} else {
|
|
// PIO Write.
|
|
for (i = 0; i < numsects; i++) {
|
|
ide_polling(channel, 0); // Polling.
|
|
port_word_out_repeat(bus, cur_addr, words);
|
|
cur_addr += (words * 2);
|
|
}
|
|
ide_write(channel, ATA_REG_COMMAND, (char[]) {ATA_CMD_CACHE_FLUSH,
|
|
ATA_CMD_CACHE_FLUSH,
|
|
ATA_CMD_CACHE_FLUSH_EXT}[lba_mode]);
|
|
ide_polling(channel, 0); // Polling.
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
uint8_t ide_access(uint8_t direction, uint8_t drive, uint32_t lba, uint8_t numsects, void *target) {
|
|
if (drive > 3
|
|
|| ide_devices[drive].reserved == 0
|
|
|| ide_devices[drive].type == IDE_ATAPI) {
|
|
return 0xF1;
|
|
}
|
|
mutex_acquire(ide_lock);
|
|
uint8_t result = ide_read_ata_access(direction, drive, lba, numsects, target);
|
|
mutex_release(ide_lock);
|
|
return result;
|
|
}
|