244 lines
6.5 KiB
C
244 lines
6.5 KiB
C
//
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// Created by rick on 02-02-21.
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//
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#ifndef NEW_KERNEL_PCI_H
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#define NEW_KERNEL_PCI_H
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#include <sys/types.h>
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#include <myke/driver.h>
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#include <stdbool.h>
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#include <myke/attributes.h>
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#define PCI_CLASS_MASS_STORAGE 0x01
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#define PCI_CLASS_BRIDGE 0x06
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// class MASS STORAGE 0x01
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#define PCI_SUB_CLASS_IDE 0x01
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// class BRIDGE 0x06
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#define PCI_SUB_CLASS_PCI_PCI_BRIDGE_4 0x04
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#define PCI_SUB_CLASS_PCI_PCI_BRIDGE_9 0x09
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#define PCI_REGISTER_OK 0
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#define PCI_REGISTER_ERR_FULL (-1)
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#define PCI_VALIDATE_OK 0
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#define PCI_VALIDATE_FAIL 1
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#define PCI_INIT_OK 0
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#define PCI_INIT_FAIL 1
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#define PCI_USE_OK 0
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#define PCI_USE_FAIL 1
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#define PCI_HEADER_TYPE_MULTI_FUNC 0x80
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#define PCI_HEADER_TYPE_ENDPOINT 0x00
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#define PCI_HEADER_TYPE_PCI_PCI_BRIDGE 0x01
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#define PCI_HEADER_TYPE_PCI_CARDBUS_BRIDGE 0x02
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#define PCI_CONFIG_VENDOR_ID 0x00
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#define PCI_CONFIG_DEVICE_ID 0x02
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#define PCI_CONFIG_COMMAND 0x04
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#define PCI_CONFIG_STATUS 0x06
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#define PCI_CONFIG_REVISION_ID 0x08
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#define PCI_CONFIG_PROG_IF 0x09
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#define PCI_CONFIG_SUBCLASS 0x0A
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#define PCI_CONFIG_CLASS_CODE 0x0B
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#define PCI_CONFIG_CACHE_LINE_SIZE 0x0C
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#define PCI_CONFIG_LATENCY_TIMER 0x0D
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#define PCI_CONFIG_HEADER_TYPE 0x0E
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#define PCI_CONFIG_BIST 0x0F
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#define PCI_CONFIG_BAR0 0x10
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#define PCI_CONFIG_BAR1 0x14
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#define PCI_CONFIG_BAR2 0x18
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#define PCI_CONFIG_BAR3 0x1C
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#define PCI_CONFIG_BAR4 0x20
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#define PCI_CONFIG_BAR5 0x24
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#define PCI_CONFIG_CARDBUS_CIS_P 0x28
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#define PCI_CONFIG_SUBSYSTEM_VENDOR_ID 0x2C
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#define PCI_CONFIG_SUBSYSTEM_ID 0x2E
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#define PCI_CONFIG_EXPANSION_ROM_ADDR 0x30
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#define PCI_CONFIG_CAP_POINTER 0x34
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#define PCI_CONFIG_INTERRUPT_LINE 0x3C
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#define PCI_CONFIG_INTERRUPT_PIN 0x3D
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#define PCI_CONFIG_MAX_GRANT 0x3E
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#define PCI_CONFIG_MAX_LATENCY 0x3F
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// header type 1
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#define PCI_CONFIG_PRIMARY_BUS_NUMBER 0x18
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#define PCI_CONFIG_SECONDARY_BUS_NUMBER 0x19
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#define PCI_CONFIG_SUBORDINATE_BUS_NUMBER 0x1A
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#define PCI_CONFIG_SECONDARY_LATENCY_TIMER 0x1B
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#define PCI_CONFIG_IO_BASE 0x1C
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#define PCI_CONFIG_IO_LIMIT 0x1D
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#define PCI_CONFIG_SECONDARY_STATUS 0x1E
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#define PCI_CONFIG_MEMORY_BASE 0x20
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#define PCI_CONFIG_MEMORY_LIMIT 0x22
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#define PCI_CONFIG_MEMORY_BASE_UPPER 0x28
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#define PCI_CONFIG_MEMORY_LIMIT_UPPER 0x2C
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#define PCI_CONFIG_IO_BASE_UPPER 0x30
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#define PCI_CONFIG_IO_LIMIT_UPPER 0x32
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#define PCI_CONFIG_EXPANSION_ROM 0x38
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#define PCI_CONFIG_BRIDGE_CONTROL 0x3E
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#define PCI_INTERRUPT_LINE_DISABLED 0xff
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typedef struct pci_device pci_device;
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typedef uint8_t (*pci_driver_use)(const pci_device *);
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typedef uint8_t (*pci_driver_validate)(const pci_device *);
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typedef uint8_t (*pci_driver_initialize)(pci_device *);
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struct pci_driver {
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const char *name;
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const char *description;
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struct {
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uint8_t class;
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uint8_t subclass;
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uint8_t interface;
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uint16_t vendor;
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uint16_t device;
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} match;
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struct {
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bool class: 1;
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bool subclass: 1;
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bool interface: 1;
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bool vendor: 1;
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bool device: 1;
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} mask;
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struct {
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bool direct_use: 1;
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bool validatable: 1;
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bool initialisable: 1;
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};
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pci_driver_use use;
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pci_driver_validate validate;
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pci_driver_initialize initialize;
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} __attribute__((__aligned__(STRUCT_ALIGNMENT)));
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#define PCI_DRIVER(order) GENERIC_DRIVER(pci_driver, order)
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typedef struct {
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uint32_t address;
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uint32_t size;
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uint8_t present: 1;
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uint8_t is_io_space: 1;
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uint8_t type: 2;
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uint8_t prefetchable: 1;
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} bar_info;
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typedef struct pci_device {
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uint8_t bus;
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uint8_t slot;
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uint8_t func;
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union {
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struct {
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uint16_t vendorId;
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uint16_t deviceId;
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};
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uint32_t config_line_0;
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};
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union {
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struct {
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uint8_t revisionId;
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uint8_t programInterface;
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uint8_t subclass;
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uint8_t class;
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};
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uint32_t config_line_2;
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};
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union {
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struct {
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uint8_t cacheLineSize;
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uint8_t latencyTimer;
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uint8_t headerType;
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uint8_t bist;
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};
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uint32_t config_line_3;
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};
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bar_info bar0;
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bar_info bar1;
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bar_info bar2;
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bar_info bar3;
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bar_info bar4;
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bar_info bar5;
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const struct pci_driver *pci_driver;
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struct {
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uint8_t present: 1;
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} device_state;
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struct {
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uint8_t initialized: 1;
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} driver_state;
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} pci_device;
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typedef union {
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uint16_t value;
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struct {
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bool io_space: 1;
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bool mem_space: 1;
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bool bus_master: 1;
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bool special_cycles: 1;
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bool mem_write_invalidate_enable: 1;
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bool vga_palette_snoop: 1;
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bool parity_error_response: 1;
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uint8_t reserved: 1;
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bool serr_enable: 1;
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bool fast_b2b_enable: 1;
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bool interrupt_disable: 1;
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uint8_t reserved2: 5;
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} packed command;
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} pci_command_register_t;
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typedef union {
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uint16_t value;
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struct {
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uint8_t reserved: 3;
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bool interrupt_status: 1;
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bool capabilities_list: 1;
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bool speed_66mhz_capable: 1;
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uint8_t reserved2: 1;
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bool fast_b2b_capable: 1;
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bool master_data_parity_error: 1;
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uint8_t devsel_timing: 2;
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bool signaled_target_abort: 1;
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bool received_target_abort: 1;
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bool received_master_abort: 1;
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bool signaled_system_error: 1;
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bool detected_parity_error: 1;
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} packed status;
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} pci_status_register_t;
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void pci_print_info();
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void pci_dump_caps();
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#ifdef ENABLE_PCIPP
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void pci_pretty_print();
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#endif
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void pci_init_drivers();
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void pci_scan();
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uint32_t pci_config_read_double_word(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
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uint16_t pci_config_read_word(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
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uint8_t pci_config_read_byte(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
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void pci_config_write_double_word(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint32_t value);
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void pci_config_write_word(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint16_t value);
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void pci_config_write_byte(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint8_t value);
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void pci_init_bar(pci_device *device, uint8_t bar_index);
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#endif //NEW_KERNEL_PCI_H
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