// // Created by rick on 28-01-21. // #include "serial.h" #include #include #define SERIAL_INTERRUPT_DATA_AVAILABLE (1 << 0) #define SERIAL_INTERRUPT_TRANSMITTER_EMPTY (1 << 1) #define SERIAL_INTERRUPT_BREAK_ERROR (1 << 2) #define SERIAL_INTERRUPT_STATUS_CHANGE (1 << 3) #define LINE_STATUS_DATA_READY (1 << 0) #define LINE_STATUS_OVERRUN_ERROR (1 << 1) #define LINE_STATUS_PARITY_ERROR (1 << 2) #define LINE_STATUS_FRAMING_ERROR (1 << 3) #define LINE_STATUS_BREAK_INDICATOR (1 << 4) #define LINE_STATUS_TRANSMITTER_HOLDING_REGISTER_EMPTY (1 << 5) #define LINE_STATUS_TRANSMITTER_EMPTY (1 << 6) #define LINE_STATUS_IMPENDING_ERROR (1 << 7) #define LINE_CONTROL_DATA_BITS_5 (0b00) #define LINE_CONTROL_DATA_BITS_6 (0b01) #define LINE_CONTROL_DATA_BITS_7 (0b10) #define LINE_CONTROL_DATA_BITS_8 (0b11) #define LINE_CONTROL_STOP_BITS_1 (0 << 2) #define LINE_CONTROL_STOP_BITS_1_5_2 (1 << 2) #define LINE_CONTROL_PARTY_NONE (0b000 << 3) #define LINE_CONTROL_PARTY_ODD (0b001 << 3) #define LINE_CONTROL_PARTY_EVEN (0b010 << 3) #define LINE_CONTROL_PARTY_MARK (0b101 << 3) #define LINE_CONTROL_PARTY_SPACE (0b111 << 3) #define LINE_CONTROL_DIVISOR (1 << 7) #define FIFO_CONTROL_ENABLE (1 << 0) #define FIFO_CONTROL_CLEAR_RECEIVE (1 << 1) #define FIFO_CONTROL_CLEAR_TRANSMIT (1 << 2) #define FIFO_CONTROL_DMA_MODE_SELECT (1 << 3) // reserved #define FIFO_CONTROL_64_BYTE_ENABLE (1 << 5) #define FIFO_CONTROL_TRIGGER_LEVEL_1_BYTE (0b00 << 6) #define FIFO_CONTROL_TRIGGER_LEVEL_4_BYTE (0b01 << 6) #define FIFO_CONTROL_TRIGGER_LEVEL_8_BYTE (0b10 << 6) #define FIFO_CONTROL_TRIGGER_LEVEL_14_BYTE (0b11 << 6) #define MODEM_CONTROL_DATA_TERMINAL_READY (1 << 0) #define MODEM_CONTROL_REQUEST_TO_SEND (1 << 1) #define MODEM_CONTROL_AUX_OUTPUT_1 (1 << 2) #define MODEM_CONTROL_AUX_OUTPUT_2 (1 << 3) #define MODEM_CONTROL_LOOPBACK_MODE (1 << 4) #define MODEM_CONTROL_AUTOFLOW_CONTROL_ENABLED (1 << 5) int serial_init() { port_byte_out(PORT_SERIAL_0 + PORT_SERIAL_INTERRUPT, 0); // Disable all interrupts port_byte_out(PORT_SERIAL_0 + PORT_SERIAL_LINE_CONTROL, LINE_CONTROL_DIVISOR); // Enable DLAB (set baud rate divisor) port_byte_out(PORT_SERIAL_0 + PORT_SERIAL_DLAB_LSB, 0x03); // Set divisor to 3 (lo byte) 38400 baud port_byte_out(PORT_SERIAL_0 + PORT_SERIAL_DLAB_MSB, 0x00); // (hi byte) port_byte_out(PORT_SERIAL_0 + PORT_SERIAL_LINE_CONTROL, LINE_CONTROL_DATA_BITS_8); // 8 bits, no parity, one stop bit port_byte_out(PORT_SERIAL_0 + PORT_SERIAL_INTERRUPT_ID_FIFO, FIFO_CONTROL_ENABLE | FIFO_CONTROL_CLEAR_RECEIVE | FIFO_CONTROL_CLEAR_TRANSMIT | FIFO_CONTROL_TRIGGER_LEVEL_14_BYTE); // Enable FIFO, clear them, with 14-byte threshold port_byte_out(PORT_SERIAL_0 + PORT_SERIAL_MODEM_CONTROL, MODEM_CONTROL_DATA_TERMINAL_READY | MODEM_CONTROL_REQUEST_TO_SEND | MODEM_CONTROL_AUX_OUTPUT_2); // IRQs enabled, RTS/DSR set port_byte_out(PORT_SERIAL_0 + PORT_SERIAL_MODEM_CONTROL, MODEM_CONTROL_REQUEST_TO_SEND | MODEM_CONTROL_AUX_OUTPUT_1 | MODEM_CONTROL_AUX_OUTPUT_2 | MODEM_CONTROL_LOOPBACK_MODE); // Set in loopback mode, test the serial chip port_byte_out(PORT_SERIAL_0 + PORT_SERIAL_DATA, 0xAE); // Test serial chip (send byte 0xAE and check if serial returns same byte) // Check if serial is faulty (i.e: not same byte as sent) if (port_byte_in(PORT_SERIAL_0 + PORT_SERIAL_DATA) != 0xAE) { return 1; } // If serial is not faulty set it in normal operation mode // (not-loopback with IRQs enabled and OUT#1 and OUT#2 bits enabled) port_byte_out(PORT_SERIAL_0 + PORT_SERIAL_MODEM_CONTROL, MODEM_CONTROL_DATA_TERMINAL_READY | MODEM_CONTROL_REQUEST_TO_SEND | MODEM_CONTROL_AUX_OUTPUT_1 | MODEM_CONTROL_AUX_OUTPUT_2); return 0; } int is_transmit_empty() { return port_byte_in(PORT_SERIAL_0 + PORT_SERIAL_LINE_STATUS) & LINE_STATUS_TRANSMITTER_HOLDING_REGISTER_EMPTY; } void write_serial(char a) { while (is_transmit_empty() == 0); port_byte_out(PORT_SERIAL_0 + PORT_SERIAL_DATA, a); } void serial_kprint(const char *msg) { u32 i = 0; while (1) { char c = msg[i]; if (c == 0) { break; } if (c == '\n') { write_serial('\r'); } write_serial(c); i++; } }