//
// Created by rick on 02-02-21.
//

#ifndef NEW_KERNEL_PCI_H
#define NEW_KERNEL_PCI_H

#include <types.h>

#define PCI_CLASS_MASS_STORAGE 0x01

// class MASS STORAGE 1
#define PCI_SUB_CLASS_IDE 0x01

#define PCI_REGISTER_OK         0
#define PCI_REGISTER_ERR_FULL   (-1)

#define PCI_VALIDATE_OK     0
#define PCI_VALIDATE_FAIL   1

#define PCI_INIT_OK     0
#define PCI_INIT_FAIL   1

#define PCI_HEADER_TYPE_MULTI_FUNC 0x80
#define PCI_HEADER_TYPE_ENDPOINT 0x00
#define PCI_HEADER_TYPE_PCI_PCI_BRIDGE 0x01
#define PCI_HEADER_TYPE_PCI_CARDBUS_BRIDGE 0x02


#define PCI_CONFIG_VENDOR_ID            0x00
#define PCI_CONFIG_DEVICE_ID            0x02
#define PCI_CONFIG_COMMAND              0x04
#define PCI_CONFIG_STATUS               0x06
#define PCI_CONFIG_REVISION_ID          0x08
#define PCI_CONFIG_PROG_IF              0x09
#define PCI_CONFIG_SUBCLASS             0x0A
#define PCI_CONFIG_CLASS_CODE           0x0B
#define PCI_CONFIG_CACHE_LINE_SIZE      0x0C
#define PCI_CONFIG_LATENCY_TIMER        0x0D
#define PCI_CONFIG_HEADER_TYPE          0x0E
#define PCI_CONFIG_BIST                 0x0F
#define PCI_CONFIG_BAR0                 0x10
#define PCI_CONFIG_BAR1                 0x14
#define PCI_CONFIG_BAR2                 0x18
#define PCI_CONFIG_BAR3                 0x1C
#define PCI_CONFIG_BAR4                 0x20
#define PCI_CONFIG_BAR5                 0x24
#define PCI_CONFIG_CARDBUS_CIS_P        0x28
#define PCI_CONFIG_SUBSYSTEM_VENDOR_ID  0x2C
#define PCI_CONFIG_SUBSYSTEM_ID         0x2E
#define PCI_CONFIG_EXPANSION_ROM_ADDR   0x30
#define PCI_CONFIG_CAP_POINTER          0x34
#define PCI_CONFIG_INTERRUPT_LINE       0x3C
#define PCI_CONFIG_INTERRUPT_PIN        0x3D
#define PCI_CONFIG_MAX_GRANT            0x3E
#define PCI_CONFIG_MAX_LATENCY          0x3F

#define PCI_INTERRUPT_LINE_DISABLED 0xff

typedef struct pci_driver pci_driver;
typedef struct pci_device pci_device;

typedef u8 (*pci_driver_validate)(const pci_device *);
typedef u8 (*pci_driver_initialize)(pci_device *);

typedef struct pci_driver {
    const char *name;
    const char *description;
    u8 order;
    u8 pci_class;
    u8 pci_subclass;
    struct {
        u8 pci_use_subclass: 1;
    };
    pci_driver_validate validate;
    pci_driver_initialize initialize;
} pci_driver;

typedef struct {
    u32 address;
    u32 size;
    u8 present: 1;
    u8 is_io_space: 1;
    u8 type: 2;
    u8 prefetchable: 1;
} bar_info;

typedef struct pci_device {
    u8 bus;
    u8 slot;
    u8 func;
    union {
        struct {
            u16 vendorId;
            u16 deviceId;
        };
        u32 config_line_0;
    };
    union {
        struct {
            u8 revisionId;
            u8 programInterface;
            u8 subclass;
            u8 class;
        };
        u32 config_line_2;
    };
    union {
        struct {
            u8 cacheLineSize;
            u8 latencyTimer;
            u8 headerType;
            u8 bist;
        };
        u32 config_line_3;
    };
    bar_info bar0;
    bar_info bar1;
    bar_info bar2;
    bar_info bar3;
    bar_info bar4;
    bar_info bar5;
    const pci_driver *pci_driver;
    struct {
        u8 present: 1;
    } device_state;
    struct {
        u8 initialized: 1;
    } driver_state;
} pci_device;

void pci_print_info();

u32 pci_register_driver(const pci_driver *pci_driver);

void pci_sort_drivers();

void pci_init_drivers();

void pci_scan();

u32 pci_config_read_double_word(u8 bus, u8 slot, u8 func, u8 offset);

u16 pci_config_read_word(u8 bus, u8 slot, u8 func, u8 offset);

u8 pci_config_read_byte(u8 bus, u8 slot, u8 func, u8 offset);

void pci_config_write_double_word(u8 bus, u8 slot, u8 func, u8 offset, u32 value);

void pci_config_write_word(u8 bus, u8 slot, u8 func, u8 offset, u16 value);

void pci_config_write_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 value);

void pci_init_bar(pci_device *device, u8 bar_index);
#endif //NEW_KERNEL_PCI_H