//
// Created by rick on 22-08-21.
//
#include <stdbool.h>
#include <myke/cpu/pic.h>
#include <myke/drivers/ports.h>

// https://wiki.osdev.org/8259_PIC
#define ICW1_ICW4       0x01        /* ICW4 (not) needed */
#define ICW1_SINGLE     0x02        /* Single (cascade) mode */
#define ICW1_INTERVAL4  0x04        /* Call address interval 4 (8) */
#define ICW1_LEVEL      0x08        /* Level triggered (edge) mode */
#define ICW1_INIT       0x10        /* Initialization - required! */

#define ICW4_8086       0x01        /* 8086/88 (MCS-80/85) mode */
#define ICW4_AUTO       0x02        /* Auto (normal) EOI */
#define ICW4_BUF_SLAVE  0x08        /* Buffered mode/slave */
#define ICW4_BUF_MASTER 0x0C        /* Buffered mode/master */
#define ICW4_SFNM       0x10        /* Special fully nested (not) */

#define PIC_END_OF_INTERRUPT 0x20

void pic_init(uint8_t isr_offset) {
    // init both master and slave pic's
    port_byte_out(PORT_PIC_MASTER_COMMAND, ICW1_INIT | ICW1_ICW4);
    port_byte_out(PORT_PIC_SLAVE_COMMAND, ICW1_INIT | ICW1_ICW4);

    // master with ICW4 offset isr_offset, Slave on IRQ2, 8086 mode,
    // ICW2
    port_byte_out(PORT_PIC_MASTER_DATA, isr_offset); // offset master
    port_byte_out(PORT_PIC_SLAVE_DATA,  isr_offset + 8); // offset slave
    // ICW3
    port_byte_out(PORT_PIC_MASTER_DATA, 0x04); // slave PIC at IRQ2
    port_byte_out(PORT_PIC_SLAVE_DATA, 0x02); // cascade identity
    // ICW4
    port_byte_out(PORT_PIC_MASTER_DATA, ICW4_8086); // 8086 mode
    port_byte_out(PORT_PIC_SLAVE_DATA, ICW4_8086);

    // empty mask
    pic_set_mask(0);
}

void pic_set_mask(uint16_t mask) {
    port_byte_out(PORT_PIC_MASTER_DATA, mask & 0xFF);
    port_byte_out(PORT_PIC_SLAVE_DATA, mask >> 8);
}

void pic_eoi(bool slave) {
    if (slave) port_byte_out(PORT_PIC_SLAVE_COMMAND, PIC_END_OF_INTERRUPT); /* slave */
    port_byte_out(PORT_PIC_MASTER_COMMAND, PIC_END_OF_INTERRUPT); /* master */
}