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feat: refactor to use gcc types

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This commit is contained in:
Rick Rongen
2021-02-12 22:16:03 +01:00
parent 555c1177a6
commit 8f615b259c
33 changed files with 419 additions and 361 deletions
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6
kernel/cpu/cpuidx.c Normal file
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@@ -0,0 +1,6 @@
//
// Created by rick on 12-02-21.
//
#include "cpuidx.h"

83
kernel/cpu/cpuidx.h Normal file
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@@ -0,0 +1,83 @@
//
// Created by rick on 12-02-21.
//
#ifndef NEW_KERNEL_CPUIDX_H
#define NEW_KERNEL_CPUIDX_H
#include <cpuid.h>
#include <stdint.h>
enum {
CPUID_FEAT_ECX_SSE3 = 1 << 0,
CPUID_FEAT_ECX_PCLMUL = 1 << 1,
CPUID_FEAT_ECX_DTES64 = 1 << 2,
CPUID_FEAT_ECX_MONITOR = 1 << 3,
CPUID_FEAT_ECX_DS_CPL = 1 << 4,
CPUID_FEAT_ECX_VMX = 1 << 5,
CPUID_FEAT_ECX_SMX = 1 << 6,
CPUID_FEAT_ECX_EST = 1 << 7,
CPUID_FEAT_ECX_TM2 = 1 << 8,
CPUID_FEAT_ECX_SSSE3 = 1 << 9,
CPUID_FEAT_ECX_CID = 1 << 10,
CPUID_FEAT_ECX_FMA = 1 << 12,
CPUID_FEAT_ECX_CX16 = 1 << 13,
CPUID_FEAT_ECX_ETPRD = 1 << 14,
CPUID_FEAT_ECX_PDCM = 1 << 15,
CPUID_FEAT_ECX_PCIDE = 1 << 17,
CPUID_FEAT_ECX_DCA = 1 << 18,
CPUID_FEAT_ECX_SSE4_1 = 1 << 19,
CPUID_FEAT_ECX_SSE4_2 = 1 << 20,
CPUID_FEAT_ECX_x2APIC = 1 << 21,
CPUID_FEAT_ECX_MOVBE = 1 << 22,
CPUID_FEAT_ECX_POPCNT = 1 << 23,
CPUID_FEAT_ECX_AES = 1 << 25,
CPUID_FEAT_ECX_XSAVE = 1 << 26,
CPUID_FEAT_ECX_OSXSAVE = 1 << 27,
CPUID_FEAT_ECX_AVX = 1 << 28,
CPUID_FEAT_EDX_FPU = 1 << 0,
CPUID_FEAT_EDX_VME = 1 << 1,
CPUID_FEAT_EDX_DE = 1 << 2,
CPUID_FEAT_EDX_PSE = 1 << 3,
CPUID_FEAT_EDX_TSC = 1 << 4,
CPUID_FEAT_EDX_MSR = 1 << 5,
CPUID_FEAT_EDX_PAE = 1 << 6,
CPUID_FEAT_EDX_MCE = 1 << 7,
CPUID_FEAT_EDX_CX8 = 1 << 8,
CPUID_FEAT_EDX_APIC = 1 << 9,
CPUID_FEAT_EDX_SEP = 1 << 11,
CPUID_FEAT_EDX_MTRR = 1 << 12,
CPUID_FEAT_EDX_PGE = 1 << 13,
CPUID_FEAT_EDX_MCA = 1 << 14,
CPUID_FEAT_EDX_CMOV = 1 << 15,
CPUID_FEAT_EDX_PAT = 1 << 16,
CPUID_FEAT_EDX_PSE36 = 1 << 17,
CPUID_FEAT_EDX_PSN = 1 << 18,
CPUID_FEAT_EDX_CLF = 1 << 19,
CPUID_FEAT_EDX_DTES = 1 << 21,
CPUID_FEAT_EDX_ACPI = 1 << 22,
CPUID_FEAT_EDX_MMX = 1 << 23,
CPUID_FEAT_EDX_FXSR = 1 << 24,
CPUID_FEAT_EDX_SSE = 1 << 25,
CPUID_FEAT_EDX_SSE2 = 1 << 26,
CPUID_FEAT_EDX_SS = 1 << 27,
CPUID_FEAT_EDX_HTT = 1 << 28,
CPUID_FEAT_EDX_TM1 = 1 << 29,
CPUID_FEAT_EDX_IA64 = 1 << 30,
CPUID_FEAT_EDX_PBE = 1 << 31
};
static inline void cpuid(int code, uint32_t *a, uint32_t *d) {
asm volatile("cpuid":"=a"(*a), "=d"(*d):"a"(code):"ecx", "ebx");
}
/** issue a complete request, storing general registers output as a string
*/
static inline int cpuid_string(int code, uint32_t where[4]) {
asm volatile("cpuid":"=a"(*where), "=b"(*(where + 1)),
"=c"(*(where + 2)), "=d"(*(where + 3)):"a"(code));
return (int) where[0];
}
#endif //NEW_KERNEL_CPUIDX_H

4
kernel/cpu/idt.c
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@@ -7,7 +7,7 @@
idt_gate_t idt[IDT_REGISTERS];
idt_register_t idt_reg;
void set_idt_gate(int n, u32 handler) {
void set_idt_gate(int n, uint32_t handler) {
idt[n].low_offset = handler & 0xffff;
idt[n].sel = KERNEL_CS;
idt[n].always0 = 0;
@@ -16,7 +16,7 @@ void set_idt_gate(int n, u32 handler) {
}
void set_idt() {
idt_reg.base = (u32) &idt;
idt_reg.base = (uint32_t) &idt;
idt_reg.limit = IDT_REGISTERS * sizeof(idt_gate_t) - 1;
__asm__ __volatile__("lidtl (%0)" : : "r" (&idt_reg));

16
kernel/cpu/idt.h
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@@ -9,26 +9,26 @@
/* How every interrupt gate (handler) is defined */
typedef struct {
u16 low_offset; /* Lower 16 bits of handler function address */
u16 sel; /* Kernel segment selector */
u8 always0;
uint16_t low_offset; /* Lower 16 bits of handler function address */
uint16_t sel; /* Kernel segment selector */
uint8_t always0;
/* First byte
* Bit 7: "Interrupt is present"
* Bits 6-5: Privilege level of caller (0=kernel..3=user)
* Bit 4: Set to 0 for interrupt gates
* Bits 3-0: bits 1110 = decimal 14 = "32 bit interrupt gate" */
u8 flags;
u16 high_offset; /* Higher 16 bits of handler function address */
uint8_t flags;
uint16_t high_offset; /* Higher 16 bits of handler function address */
} __attribute__((packed)) idt_gate_t;
typedef struct {
u16 limit;
u32 base;
uint16_t limit;
uint32_t base;
} __attribute__((packed)) idt_register_t;
#define IDT_REGISTERS 256
void set_idt_gate(int n, u32 handler);
void set_idt_gate(int n, uint32_t handler);
void set_idt();

98
kernel/cpu/isr.c
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@@ -14,38 +14,38 @@
isr_t interrupt_handlers[256];
void isr_install() {
set_idt_gate(0, (u32) isr0);
set_idt_gate(1, (u32) isr1);
set_idt_gate(2, (u32) isr2);
set_idt_gate(3, (u32) isr3);
set_idt_gate(4, (u32) isr4);
set_idt_gate(5, (u32) isr5);
set_idt_gate(6, (u32) isr6);
set_idt_gate(7, (u32) isr7);
set_idt_gate(8, (u32) isr8);
set_idt_gate(9, (u32) isr9);
set_idt_gate(10, (u32) isr10);
set_idt_gate(11, (u32) isr11);
set_idt_gate(12, (u32) isr12);
set_idt_gate(13, (u32) isr13);
set_idt_gate(14, (u32) isr14);
set_idt_gate(15, (u32) isr15);
set_idt_gate(16, (u32) isr16);
set_idt_gate(17, (u32) isr17);
set_idt_gate(18, (u32) isr18);
set_idt_gate(19, (u32) isr19);
set_idt_gate(20, (u32) isr20);
set_idt_gate(21, (u32) isr21);
set_idt_gate(22, (u32) isr22);
set_idt_gate(23, (u32) isr23);
set_idt_gate(24, (u32) isr24);
set_idt_gate(25, (u32) isr25);
set_idt_gate(26, (u32) isr26);
set_idt_gate(27, (u32) isr27);
set_idt_gate(28, (u32) isr28);
set_idt_gate(29, (u32) isr29);
set_idt_gate(30, (u32) isr30);
set_idt_gate(31, (u32) isr31);
set_idt_gate(0, (uint32_t) isr0);
set_idt_gate(1, (uint32_t) isr1);
set_idt_gate(2, (uint32_t) isr2);
set_idt_gate(3, (uint32_t) isr3);
set_idt_gate(4, (uint32_t) isr4);
set_idt_gate(5, (uint32_t) isr5);
set_idt_gate(6, (uint32_t) isr6);
set_idt_gate(7, (uint32_t) isr7);
set_idt_gate(8, (uint32_t) isr8);
set_idt_gate(9, (uint32_t) isr9);
set_idt_gate(10, (uint32_t) isr10);
set_idt_gate(11, (uint32_t) isr11);
set_idt_gate(12, (uint32_t) isr12);
set_idt_gate(13, (uint32_t) isr13);
set_idt_gate(14, (uint32_t) isr14);
set_idt_gate(15, (uint32_t) isr15);
set_idt_gate(16, (uint32_t) isr16);
set_idt_gate(17, (uint32_t) isr17);
set_idt_gate(18, (uint32_t) isr18);
set_idt_gate(19, (uint32_t) isr19);
set_idt_gate(20, (uint32_t) isr20);
set_idt_gate(21, (uint32_t) isr21);
set_idt_gate(22, (uint32_t) isr22);
set_idt_gate(23, (uint32_t) isr23);
set_idt_gate(24, (uint32_t) isr24);
set_idt_gate(25, (uint32_t) isr25);
set_idt_gate(26, (uint32_t) isr26);
set_idt_gate(27, (uint32_t) isr27);
set_idt_gate(28, (uint32_t) isr28);
set_idt_gate(29, (uint32_t) isr29);
set_idt_gate(30, (uint32_t) isr30);
set_idt_gate(31, (uint32_t) isr31);
// Remap the PIC
port_byte_out(0x20, 0x11);
@@ -60,22 +60,22 @@ void isr_install() {
port_byte_out(0xA1, 0x0);
// Install the IRQs
set_idt_gate(32, (u32) irq0);
set_idt_gate(33, (u32) irq1);
set_idt_gate(34, (u32) irq2);
set_idt_gate(35, (u32) irq3);
set_idt_gate(36, (u32) irq4);
set_idt_gate(37, (u32) irq5);
set_idt_gate(38, (u32) irq6);
set_idt_gate(39, (u32) irq7);
set_idt_gate(40, (u32) irq8);
set_idt_gate(41, (u32) irq9);
set_idt_gate(42, (u32) irq10);
set_idt_gate(43, (u32) irq11);
set_idt_gate(44, (u32) irq12);
set_idt_gate(45, (u32) irq13);
set_idt_gate(46, (u32) irq14);
set_idt_gate(47, (u32) irq15);
set_idt_gate(32, (uint32_t) irq0);
set_idt_gate(33, (uint32_t) irq1);
set_idt_gate(34, (uint32_t) irq2);
set_idt_gate(35, (uint32_t) irq3);
set_idt_gate(36, (uint32_t) irq4);
set_idt_gate(37, (uint32_t) irq5);
set_idt_gate(38, (uint32_t) irq6);
set_idt_gate(39, (uint32_t) irq7);
set_idt_gate(40, (uint32_t) irq8);
set_idt_gate(41, (uint32_t) irq9);
set_idt_gate(42, (uint32_t) irq10);
set_idt_gate(43, (uint32_t) irq11);
set_idt_gate(44, (uint32_t) irq12);
set_idt_gate(45, (uint32_t) irq13);
set_idt_gate(46, (uint32_t) irq14);
set_idt_gate(47, (uint32_t) irq15);
set_idt(); // Load with ASM
}
@@ -122,7 +122,7 @@ void isr_handler(registers_t r) {
printf("Received interrupt: %d - %s\n", r.int_no, exception_messages[r.int_no]);
}
void register_interrupt_handler(u8 n, isr_t handler) {
void register_interrupt_handler(uint8_t n, isr_t handler) {
interrupt_handlers[n] = handler;
}

10
kernel/cpu/isr.h
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@@ -123,15 +123,15 @@ extern void irq15();
#define IRQ15 47
typedef struct {
u32 ds;
u32 edi, esi, ebp, esp, ebx, edx, ecx, eax;
u32 int_no, err_code;
u32 eip, cs, eflags, useresp, ss;
uint32_t ds;
uint32_t edi, esi, ebp, esp, ebx, edx, ecx, eax;
uint32_t int_no, err_code;
uint32_t eip, cs, eflags, useresp, ss;
} registers_t;
typedef void (*isr_t)(registers_t);
void register_interrupt_handler(u8 n, isr_t handler);
void register_interrupt_handler(uint8_t n, isr_t handler);
void isr_install();

14
kernel/cpu/timer.c
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@@ -32,14 +32,14 @@
#define PIT_CHANNEL_2 (0b10 << 6)
#define PIT_CHANNEL_READ_BACK (0b11 << 6)
u32 tick = 0;
uint32_t tick = 0;
static void timer_callback(registers_t regs) {
tick++;
}
void sleep(u32 milliseconds) {
u32 done = tick + milliseconds;
void sleep(uint32_t milliseconds) {
uint32_t done = tick + milliseconds;
while (tick != done) {
k_wait_for_interrupt();
}
@@ -53,12 +53,12 @@ void print_current_tick() {
kprint("\n");
}
int init_timer(u32 freq) {
int init_timer(uint32_t freq) {
register_interrupt_handler(IRQ0, timer_callback);
u32 divisor = 1193180 / freq;
u8 low = (u8) (divisor & 0xFF);
u8 high = (u8) ((divisor >> 8) & 0xFF);
uint32_t divisor = 1193180 / freq;
uint8_t low = (uint8_t) (divisor & 0xFF);
uint8_t high = (uint8_t) ((divisor >> 8) & 0xFF);
port_byte_out(PORT_PIT_COMMAND,
PIT_MODE_BIN | PIT_MODE_HARDWARE_SQUARE_WAVE_GENERATOR | PIT_ACCESS_MODE_LH | PIT_CHANNEL_0);
port_byte_out(PORT_PIT_DATA_0, low);

4
kernel/cpu/timer.h
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@@ -7,10 +7,10 @@
#include <types.h>
int init_timer(u32 freq);
int init_timer(uint32_t freq);
void print_current_tick();
void sleep(u32 milliseconds);
void sleep(uint32_t milliseconds);
#endif //MY_KERNEL_TIMER_H